## Verilog Language Continued

 Vector Data

In the single bit comparator example we had only two sets of 1 bit input. What if we need to design a comparator that has two sets of 2 bit input ? Verilog provides the concept of Vectors. Vectors are used to represent multi-bit busses.

A vector to represent a multi bit bus is declared as follows

reg [7:0] eightbitbus; // 8-bit reg vector with MSB=7 LSB=0

The reg [7:0] means you start with 0 at the rightmost bit to begin the vector, then move to the left. We could also declare the vector as

reg [0:7] eightbitbus; // 8-bit reg vector with MSB=0 LSB=7

In which case the LSB will be represented by leftmost bit.

Let us rewrite our comparator example, so that it now use two bit bus in place of one bit.

 ``timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Company: referencedesigner.com //////////////////////////////////////////////////////////////////////////////////module comparator2bit( input [1:0] x, input [1:0] y, output z ); assign z = (x[0] & y[0] & x[1] & y[1]) | (~x[0] & ~y[0] & x[1] & y[1]) | (~x[0] & ~y[0] & ~x[1] & ~y[1])| (x[0] & y[0] & ~x[1] & ~y[1]);endmodule  `

 ``timescale 1ns / 1ps /* StimulusExample showing two bit comparatorreferencedesigner.com*/ module stimulus1;  reg [1:0] x; reg [1:0] y; wire z;   // Instantiate the Unit Under Test (UUT) comparator2bit uut ( .x(x), .y(y), .z(z) ); initial begin // Initialize Inputs x = 2'b00; y = 2'b00;  // Wait 100 ns for global reset to finish #100; #50 x =2'b01; #50 y =2'b01; #50 y =2'b11; #50 x =2'b11;  end  initial begin\$monitor("x=%d,y=%d,z=%d \n",x,y,z);end endmodule  `

This example produces the following in console
``` ```
x=0,y=0,z=1

x=1,y=0,z=0

x=1,y=1,z=1

x=1,y=3,z=0

x=3,y=3,z=1
``````
` ` Note that x =3 means 11 in binary.