Verilog Language Continued


Vector Data

In the single bit comparator example we had only two sets of 1 bit input. What if we need to design a comparator that has two sets of 2 bit input ? Verilog provides the concept of Vectors. Vectors are used to represent multi-bit busses.

A vector to represent a multi bit bus is declared as follows

reg [7:0] eightbitbus; // 8-bit reg vector with MSB=7 LSB=0

The reg [7:0] means you start with 0 at the rightmost bit to begin the vector, then move to the left. We could also declare the vector as

reg [0:7] eightbitbus; // 8-bit reg vector with MSB=0 LSB=7

In which case the LSB will be represented by leftmost bit.

Let us rewrite our comparator example, so that it now use two bit bus in place of one bit. 

  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: referencedesigner.com 
  4. //////////////////////////////////////////////////////////////////////////////////
  5. module comparator2bit(
  6.     input [1:0] x,
  7.     input [1:0] y,
  8.     output z
  9.     );
  10.  
  11. assign z = (x[0] & y[0] & x[1] & y[1]) | 
  12.          (~x[0] & ~y[0] & x[1] & y[1]) |
  13. 			(~x[0] & ~y[0] & ~x[1] & ~y[1])|
  14. 			 (x[0] & y[0] & ~x[1] & ~y[1]);
  15. endmodule
  16.  
  17.  
 




  1. `timescale 1ns / 1ps
  2.  
  3. /* Stimulus
  4. Example showing two bit comparator
  5. referencedesigner.com
  6. */
  7.  
  8. module stimulus1;
  9.  
  10. 	reg [1:0] x;
  11. 	reg [1:0] y;
  12.    wire z; 
  13.  
  14. 	// Instantiate the Unit Under Test (UUT)
  15. 	comparator2bit uut (
  16. 		.x(x),
  17. 		.y(y),
  18. 		.z(z)
  19. 	);
  20. 	initial begin
  21. 		// Initialize Inputs
  22. 		x = 2'b00;
  23.       y = 2'b00;
  24.  
  25. 		// Wait 100 ns for global reset to finish
  26. 		#100;
  27. 		#50 x =2'b01;
  28. 		#50 y =2'b01;
  29. 		#50 y =2'b11;
  30. 		#50 x =2'b11;
  31.  
  32. 	end
  33.  
  34.  
  35. initial begin
  36. $monitor("x=%d,y=%d,z=%d \n",x,y,z);
  37. end
  38.  
  39. endmodule
  40.  
  41.  


This example produces the following in console 
 
x=0,y=0,z=1 

x=1,y=0,z=0 

x=1,y=1,z=1 

x=1,y=3,z=0 

x=3,y=3,z=1
Note that x =3 means 11 in binary.