## Verilog Quiz

Verilog Quiz # 8

Eight Quiz

Q1. Full connection describes connection between

A . Each bit of source to each bit of destination
B . Each bit of source to every bit of destination
C . Every bit of source to each bit of destination
D . Only A
E . Only B
F. B & C

Q2. For full connection given below how many parallel connections are possible

```//a[31:0] is a 32 bit vector and out is [10:0] bit vector specify (a *> out) = 9; endspecify ```

A . 32
B . 100
C . 320
D. 352

Q3. What is the minimum FIFO depth for below specification

Writing clock =30MHz
Burst Size=B=30
8 idle clock cycles for reading

A . 29.9
B . 25
C . 25.2
D. 37.2

Q4. State table in UDP can contain

A . 0,1
B . 0,1,z
C . 0,1,x
D. 0,1,x,z

Q5. In UDP

A . Multiple input and one output is permitted
B . One input and multiple output is permitted
C . Multiple input and multiple output is permitted
D. One input and one output is permitted

Q6. In non blocking assignment

A . Evaluates all RHS for current time unit and assign to LHS at current time
B . Evaluates all RHS for current time unit and assign to LHS at the end of time unit
C . Whole statement is done before control passes to next statement
D. None

Q7. For the below code segment given below

```always @(posedge clk) a=b; always @(posedge clk) b=a;```

A . Values of a and b are swapped
B . Values of a and b cannot be swapped
C . Values of a and b can be swapped depending on simulator
D. Can’t determine

Q8. For the below code segment choose the right answer, if a is 1’bx or 1’bz

``` reg a; casex (a) 1'b0 : statement1; 1'b1 : statement2; 1'bx : statement3; 1'bz : statement4; endcase ```

A . statement 1 is executed
B . procedural continuous assignment
C . blocking assignment
D. nonblocking assignment

Q9. Clock skew is the phenomenon of

A . Synchronous circuit
B . Asynchronous circuit
C . Both
D. None

Q10. Cycle based simulation is useful for

A . Synchronous circuit
B . Asynchronous circuit
C . Both
D. None

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