## Verilog Blocking vs non blocking

If there are multiple assignment statements in the always block in verilog then they can be done in two different ways

1. Blocking using =
2. Non Blocking using <=

We will first consider an example usage of Blocking and non blocking assignments in initial statements. The initial statements are not synthesisable and these example are only for the test benches.

But it is very good for our initial learling. So first the blocking assignment statements using =.

 ````timescale 1ns/1ps module blocking; reg p,q,r ;   initial begin p = #10 1'b1;// Executed at time t = 10 units q = #30 0'b0;// Executed at time t = 10 + 30 = 40 units r = #20 1'b1;// Executed at time t = 40 + 20 = 60 units end initial begin \$monitor ("%d p=%1b q=%1b r=%1b",\$time, p,q,r); end endmodule```

In the blocking assignment statement, the three statements in the initial block

 ```p = #10 1'b1; q = #30 0'b0; r = #20 'b1;```

are executed sequentially - one after the other. The first statement

 ` p = #10 1'b1;`

"blocks" the execution of the other two statements. Hence the name blocking assignment. Notice that we have used a delay of 10 units in this statement. As we said earlier, this is not something that will synthesise but is very useful for our initial understanding.

So for 10 time units, other assign statements in this initial block are blocked from execution. After 10 time units, p is assigned value of 1'b1. Right after that, it is time for the next blocking assign statement

 `q = #30 1'b0;`

Again this blocks any statement from execution, this this statement is executed. Here, q is assigned a value of 1'b0, after a delay of 30 time units. So essentially, q gets assigned a value of 1'b0 after a time of 40 units. Finally r gets assigned a value of 1'b1 at time t = 60 units. Here is the result of the simulation

 ```0 p=x q=x r=x 10 p=1 q=x r=x 40 p=1 q=0 r=x 60 p=1 q=0 r=1 ```

Initially the values of p, q and r are all undecided 'x'. In blocking assignments the statements are executed sequentially one after the other.

Now we will write the same example using non blocking assignment

 ````timescale 1ns/1ps module nonblocking; reg p,q,r ;   initial begin p <= #10 1'b1;// Executed at time t = 10 units q <= #30 1'b0;// Executed at time t = 10 + 30 = 40 units r <= #20 1'b1;// Executed at time t = 40 + 20 = 60 units end initial begin \$monitor ("%d p=%1b q=%1b r=%1b",\$time, p,q,r); end endmodule```

Here is the result of running this

 ```0 p=x q=x r=x 10 p=1 q=x r=x 20 p=1 q=x r=1 30 p=1 q=0 r=1```

Let us understand it now. As soon as it enters the initial begin block, it sees the there statements

 ``` p <= #10 1'b1; q <= #30 1'b0; r <= #20 1'b1;```

and starts the operation on the Right Hand Side of <= simultaneously. The first execution statement

 `p <= #10 1'b1;`

does not block the execution of the remaining two statements. So all three statements start execution at t = 0 second. The RHS statement of the first one completes at t = 10 units, of the seconf one at t = 30 units and of the third unit at t = 20 units.

And therefore when we use the monitor statement to display values, the p is seen assigned to 1'b0 at t = 10 seconds. The next one seed to be assigned is the third statement r = 1'b1 at t = 20 units. Finally at t = 30 units, the second statement t = 30 units.

Notice that initially the values of p. q and r are 1'bx or undetermined.

Although this is not code that will synthesize into something, it helps in our understanding of the blocking and non blacking statement.
We have some more topics on Blocking versus non blocking here .