## UDP

 User Defined Primitive

In the last page we saw how to create a single bit comparator using gate level modeling with predefined primitives. The use of the gates can becomes cumbursome if the number of gates are large. It also becomes hard to follow the code intuitively. Fortunately verilog also provide the concept of User Defined Primitives ( UDPs). Using UDPs we define the function of a combinational logic using table.

Here is the 1 bit comparator example using the UDP

 ``timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Example of comparator using UDP Table//////////////////////////////////////////////////////////////////////////////////module comparator( input x, input y, output z);compare c0(z, x, y);endmodule primitive compare(out, in1, in2); output out; input in1,in2; table// in1 in2 : out 0 0 : 1; 0 1 : 0; 1 0 : 0; 1 1 : 1; endtableendprimitive `

This example does the same fuction as the previous example, but we have used primitive gates in this example. Notice how the verilog code gets simplified by the use of the udp tables/

 Explanation

A new primitive is defined using the primitive keyword. It has an output and a list of inputs as its argument.

 `primitive compare(out, in1, in2);output out;input in1,in2;`

The definition of the primitive is followed by a table definition. The Table definition starts with keyword table and ends with keyword endtable

 `table// in1 in2 : out0 0 : 1;0 1 : 0;1 0 : 0;1 1 : 1;endtable`

Inside the table definition we define the primitive behavior with a number of rows. Each row has values of the inputs separated by whitespaces, followed by semicolon, followed by the output. The input values should be in the same sequence as defined in the premitive definition.

Finally the prenitive definition ends with the keyword endpremitive.

We can instantiate the primitive with the primitive name followed by and identifier name and a list of the out and inputs as in

``` compare c0(z, x, y); ```

The stimulus stays the same and it produces the same result.
 ``timescale 1ns / 1ps /* StimulusExample showing two bit comparatorreferencedesigner.com*/ module stimulus1;  reg x; reg y; wire z;   // Instantiate the Unit Under Test (UUT) comparator uut ( .x(x), .y(y), .z(z) ); initial begin // Initialize Inputs x = 0; y = 0;  // Wait 100 ns for global reset to finish #100; #50 x = 1; #60 y = 1; #70 y = 1; #80 x = 0; end  initial begin\$monitor("x=%d,y=%d,z=%d \n",x,y,z);end endmodule`

And it produces the same output
``````
x=0,y=0,z=1
x=1,y=0,z=0
x=1,y=1,z=1
x=0,y=1,z=0
```
```