Verilog Language

We will briefly go through the terminologies of the Verilog language. If you are already aware of the programming language constructs, you may skip this page and go to the next one. But it does not harm to skim through this material quickly.


When writing Verilog code, you will need to identify an object, such as an input port, a variable. An identifier is used for that purpose. In the

Looking at our previous example

In this example comparator is an identifier used to identify the module. So are x , y z , used to denote an input or an output port.

An identifier must begin with an alphabetic character or an underscore. Basically anything in the range (a-z A-Z_).
An identifier may contain alphabetic or numeric characters, the underscore or the dollar sign. Basically anything in the range (a-z A-Z 0-9 _$)

Example of Valid identifiers



Example of Invalid identifiers


Escaped Identifiers

It is possible that you need to use the characters as keywords that are ordinarily prohibited. For example, you may wish to use clock~ to represent a negative differential clock or reset# to denote a negative going reset pulse. Verilog does provide a workaround by escaping the character. Basically you add a backward slash at the beginning of a keyword and you can use any character you want. Examples

module \#differential (
input clk1,
input \clk1~,


Keywords are special words used to describe the language construct. As you can see in our above example, module, assign are keywords.


A Single line comment in Verilog starts with // Multiline comments start with /* and end with */. Always use plenty of comments to make you code more readable.

The example below shows the proper use of the multiline and single line comments

  1. /*
  2. Comparator Module for single bit comparison
  3. Written by
  4. */
  5. module comparator(
  6. input x,
  7. input y,
  8. output z
  9. );
  10. // z is a single bit comparator
  11. assign z = (~x & ~y) |(x & y);
  12. endmodule


Whitespaces are used to separate the different elements of verilog code including keywords, identifiers and variables. White spaces include space, tab, new line. Proper use of white spaces make the code more readable.
We have presented here the same code with three different styles of comments. The first one has too little white space. The second one has optimal use of white spaces and third one has excessive usage of white space

Too Little Use of White Spaces

  1. module comparator(input x input y, output z );
  2. assign z = (~x & ~y) |(x & y); endmodule

Optimal Use of White Spaces

  1. module comparator(
  2. input x,
  3. input y,
  4. output z
  5. );
  7. assign z = (~x & ~y) |(x & y);
  9. endmodule

Excessive Use of White Spaces

  1. module
  2. comparator
  3. (
  4. input x,
  5. input y,
  6. output z
  7. );
  9. assign z = (~x & ~y) |(x & y);
  11. endmodule

Case Sensitivity

Verilog is case sensitive. There are couple of things you need to keep in mind

1. All the verilog keywords are in lower case.
2. If you use an identifier that starts with upper case, it will be different from the one in lower case.

wire  // A verilog keyword
WIRE  // This will not be a verilog keyword 

We will continue to explore more of the Verilog Syntax in the next post.