Continuous Assignment Statement

Continuous assignment statements in Verlog are used to model combinational logics. By combinational logic we mean the digital logic implemmented by Boolean circuits. In combinational logic the output is a pure function only of PRESENT INPUTs.

The combinational logic is different from sequential logic where the present input depends not only upon the present input but also upon the past inputs.

In theory any combinational logic can also be implemented using primitive gates, but the continuous Assignment makes the code easier to understand at higher level of abstraction.

In verilog, continuous assignment statement is implemmented with assign statement or with wire declaration. We will first consider the assign statement.

The left-hand side of an assignment is a variable to which the right-side value is to be assigned. The left hand side must be a scalar or vector net or concatenation of both. The right-hand side of assign statement is separated by = character. Right hand side can be a net, a reg or any expression that evaluates a value.

One caution - while the right hand side can contain reg type, the left hand side can not.

In the example below and AND gate is realized using the continuous assignment statement.

Example 1

wire out
assign out = input1 & input2;

Continuous assignments drive values into the nets whenever the right-hand side value changes, The continuous assignments are always active and assignments occur whenever the right-hand side operands changes.

In the example below shows vector continuous assignment statement.

Example 2

wire [7:0] Data;
assign Data[7:0] = input_A[7:0] ^ input_B[7:0] ;

The left hand side can also be a concatenation of vectors, or scalars or vector and scalars. The example below shows the implementation of full adder using vector and scalar in the assignment operation.

Example 3

assign {c_out, sum[7:0]} = Input_A[7:0]+ Input_B[7:0]+c_in;

The assignment operation can also be done during the wire declaration. The following example gives the same result as the Example 1

Example 4

wire out = input1 & input2;
The output variable or the left hand side of a continuous assignment statement can not be a reg . So the following will be incorrect.

Example 5

module gate(out, in1,in2);
input  in1,in2;
output reg out;
assign out =  in1 & in2;
The continuous assignment can NOT be used in an always or initial block. So the following will be incorrect

Example 6

module gate(out, in1,in2);
input  in1,in2;
output  out;
always @ ( in1, in2)
assign out =  in1 & in2;
The continuous assignment statement can be used to mode a tristate buffer as in following example

Example 7

module tristatebuffer();
reg data_in, enable;
wire pad;
assign pad = (enable) ? data_in : 1'bz;
When enable is 1, the pad is assigned the value of data_in, and when enable is 0, the pad is tristated.

A delay can be specified in the continuous assignment statement. In the following example, the output cout is assigned 12 nano seconds after the inputs.

Example 8

module adder (cout, sum, a, b, cin);
  output       cout;
  output [3:0] sum;
  input  [3:0] a, b;
  input        cin;
  assign #12 {cout, sum} = a + b + ci;

Delays are, however, not synthesysable.