Cadence Allehro Design Entry Concept HDL Tutorial

This tutorial by is intended for beginners in who wish to learn designing a Schematics using Cadence Design Entry HDL ( earlier known a Concept HDL). The Design Entry HDL is the Cadence's natural choice for Schematics Entry. OrCAD is another popular tool ( also part of the Allegro line) for the Schematics entry. If you are interested in learning schematics entry using OrCAD, you can check the orcad tutorial here.


If you are already familiar with the process of circuit and PCB design, you may skip this page. Otherwise, getting a quick overview of the circuit and PCB design process will help you understand basics f the process.

1. Any given electronic design uses a large number of distinct components such as resistors, capacitors, ICs, sockets, connectors, diodes, transistors. The purpose of the Schematics capture is to connect these components in a way that gives desired functionality to the circuit.

In actual practice following are the main categories of the components used

Commodity components like Resistors, Capacitors, Inductors, Ferrite Beads
Diodes, Transistors, FETS, LEDs
Connectors, Headers

2. For each component, you will be required to create a Symbol in the Library. Symbol is a physical view of the component that includes all the pins of the component and one or more properties. Each component must have an associated footprint which is used for Layout.

In many cases, you should already have the Symbols used in previous projects. It is advisible to reuse as much of the existing design as possible. This tutorial will also guide you how to create a new Symbol. It is very important that the symbol you create in the library matches the component according to its datasheet. You must double check the pin numbers in the Symbol you create with the datasheet of the component.

3. Once you have symbols of all the components, you add them in your Schematics and connect them with wires. You will also add the Power and Ground as necessary.

4. The next step is to check your Schematics for design errors and if no errors are found, generate a net list. The netlist describes the connectivity of an electronic design. The net list is used by the Allegro Layout tools for importing.

5. You will also edit a number of properties of the symbols required by the Allegro Layout. This includes for example, the length matching constraints and differential nets assignments.

6. The Schematics can also be used for Digital or Analog Simulations.

There are a number of other concepts and powerful functions provided by the Design Entry HDL tool, but we will keep ourselves restricted to the only a few basic things. We will focus on learning the process of generating a very simple Schematics. We will state our goal in the next page and will accomplish the goal in the next few pages that follow it.