VHDL TUTORIAL | Verificatiom


If our code is correct it will produce the result accoring to the following table

Table: A one bit comparator



Input x Input y Output z
0 0 1
0 1 0
1 0 0
1 1 1


Every VHDL implementation goes though extensive verification. How do we verify the circuit behaves as expected ? We basically provide stimulus to the circuit at its input port and check its output. We change the input and check the output again. We continue doing it till we exhaust all possible inputs. If output under all conditions is as expected, the circuit stands verified.

Here is how a stimulus verification code looks like 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
--referencedesigner.com tutorial
 
ENTITY stimulus IS
END stimulus;
 
ARCHITECTURE behavior OF stimulus IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT comparator
    PORT(
         x : IN  std_logic;
         y : IN  std_logic;
         z : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal x : std_logic := '0';
   signal y : std_logic := '0';

 	--Outputs
   signal z : std_logic;
   constant period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: comparator PORT MAP (
          x => x,
          y => y,
          z => z
        );

   -- Stimulus process
   stim_proc: process
   begin		
   
      wait for period;
		x <= '1';
		wait for period;
		y <= '1';
		 wait for period;
		x <= '0';
		wait for period;
		y <= '0';
		wait for period;

      wait;
   end process;

END;



We will try to make you understand the code. The code 


  COMPONENT comparator
    PORT(
         x : IN  std_logic;
         y : IN  std_logic;
         z : OUT  std_logic
        );
    END COMPONENT;


delares a comparator. Do not worry about understanding it. Things will become clearer as you keep reading.

The code 

 constant period : time := 10 ns;

defines the unit of time which we will use to change the values of the inputs x and y at certain periods of time

The code 

		wait for period;
		x <= '1';
		wait for period;
		y <= '1';
		 wait for period;
		x <= '0';
		wait for period;
		y <= '0';
		wait for period;

changes the values of x and y at defined intervals of time. 




If we simulate this code with Xilinx Simulation tool, we get a waveform that looks as follows








In the next page we will see how to test this code using the simulation with Xilinx tool.