VHDL TUTORIAL for beginners
We hope before you read this tutorial, you have downloaded the Xilinx ISE free version - which can be used to learn verilog. It has a nice Simulator as well. if your download is still not finished, do not worry, and continue to read the tutorial. You will still have a good understanding of the verilog concepts.
Once the download finishes, install the Xilinx ISE. There are two things that need to mentioned.
1. Choose the ISE Webpack+Viviado Webpack for installtion. This is the free version. Others are paid versions.
2. Once you finish the installation, you will be asked to register to get the license. When appling for the license you need to select "Get Free ISE Webpack License".
This will complete the installation. We will now start learning the VHDL itself. Notice that you can still follow this tutorial even if you have not installed the tool, but it is a good idea to practice by writing, compiling and running the actual software.
Let us start with the design of a simple comparator to start understanding the VHDL language. This will also be out "Hello World" of the HDL. Let us take a look at the following table which describes the behavious of a comparator circuit
Table: A one bit comparator
| Input x | Input y | Output z |
| 0 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 | 0 |
| 1 | 1 | 1 |
Basically when both the inputs x and y are same, the output z is 1. When the inputs are unequal, the output is 0.
We can describe the circuit using and, not and or gates using the following equation.
z = (~x & ~y) |(x & y);
where ~x and ~y represent the complements of x and y respectively.
The following shows a circuit that implements this logic.
And here is the VHDL code that implements this logic
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Referencedesigner.com VHDL tutorial
entity comparator is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end comparator;
architecture Behavioral of comparator is
begin
z <= (x AND y) or ( (NOT x) AND (NOT y)) ;
end Behavioral;
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We will try to make you understand what VHDL is - in a matter of one day. At least you should be able to compile and run verilog code ( Kind of Hello World of verilog). We hope that this is something you will be able to achieve within next few pages. Throoughout this tutorial we will present you enough examples and exercises so that you have a good grip over the language as well as the verilog concepts.
While VHDL executes has concurrent blocks executing in parallel, it is still similar to software programming language like C and Ada.
If you have closely watched the schematics above and the verilog code below it, you must have appreciated how VHDL simplifies the process. Before the advent of VHDL, everything was done using schematics. The Schematics were error-prone, diffult to verify and had long process of design, verfification, fix, redesign and re verify.
When VHDL the whole dimension and processo of hardware circuit design changed. This provided a new way of looking at and designg the circuiyt. Verilog design is more like a software programming, but, you must also have a strong understanding of the circuit that works behing the code.
Let us now understand the code. Take a loook at
entity comparator is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC);
end comparator;
VHDL consists of entities ( In verilog it is called modules). Inside the entities we have a list of ports ( or pins). A port can be an input ( defined with keyword im) or an output ( defined with keyword out) depending upon its direction. A pin can also be defined as bidirectional using inout.
Let us now take a look at the assignment statement
z <= (x AND y) or ( (NOT x) AND (NOT y)) ;
This implements a combinational logic. An assignment statement is used for modeling only combinational logic. The statement in the assign statement is executed continuously ( as against those that trigger on a clock).An assign statement is also called 'continuous assignment statement'.
This statement implements the comparator logic that we had shown earlier in example
In the next page we will see how to test this code using the simulation.