Verilog Language Continued
Vector Data |
In the single bit comparator example we had only two sets of 1 bit input. What if we need to design a comparator that has two sets of 2 bit input ? Verilog provides the concept of Vectors. Vectors are used to represent multi-bit busses.
A vector to represent a multi bit bus is declared as follows
reg [7:0] eightbitbus; // 8-bit reg vector with MSB=7 LSB=0
The reg [7:0] means you start with 0 at the rightmost bit to begin the vector, then move to the left. We could also declare the vector as
reg [0:7] eightbitbus; // 8-bit reg vector with MSB=0 LSB=7
In which case the LSB will be represented by leftmost bit.
Let us rewrite our comparator example, so that it now use two bit bus in place of one bit.
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This example produces the following in console
x=0,y=0,z=1
x=1,y=0,z=0
x=1,y=1,z=1
x=1,y=3,z=0
x=3,y=3,z=1
Note that x =3 means 11 in binary.