Verilog Language Continued


Verilog Modules

To allow the concept of heirarchichal building blocks, verilog provides the concept of modules. In the comparator example we presented we had only one module. But a real life design will have several modules. For example a single bit comparator could have been used at several places in the whole design. A Verilog prvides the concept of module instantiation. We will discuss about the complex modules hierarchy later.

Ports

Modules are connected by Ports. A port can be an input, an output or an inout.


Summing up the modules and Ports

Typically a module and a port is declared as in the example below. 

  1. module comparator(
  2.     input x,
  3.     input y,
  4.     output z
  5.     );
  6.  
  7. assign z = (~x & ~y) |(x & y);
  8.  
  9. endmodule



The module definition starts with the keyword module followed by the module name which is an identifier to identify the name of the module. The module contains a list of the input and output port and enclosed by paranthesis and ";". The module definition is succeded by a list of codes describing the behaviour of the module. Finally the module definition ends with the keyword endmodule.
Notice that the port directions could also be defined outside the module declaratin as in the following examle - a practice we will not follow. It is being presented here to make you aware of the fact that such coding styles still exists and at times you may have to understand it. 

  1. module comparator( 
  2.    x,
  3.    y,
  4.    z)
  5.     );
  6. 	input x,
  7.     input y,
  8.     output z
  9. assign z = (~x & ~y) |(x & y);
  10. endmodule




Rules of Connecting Ports Ports

There are certain rules that must be followed when connecting and input , output and the inout ports

Input Ports Internally the input ports must always be of type net. Externally the inputs can connect to a variable of type reg or net.
Outputs Internally output port can be net or reg. Externally the outputs must connect to a variable of type net.
Inouts The Inout port must always be of type net internally or externally .