Verilog TUTORIAL | Verificatiom


If our code is correct ,it will produce the result accoring to the following table

Table: A one bit comparator

Input x Input y Output z
0 0 1
0 1 0

1 0 0
1 1 1



Every verilog implementation goes though extensive verification. How do we verify the circuit behaves as expected ? We basically provide stimulus to the circuit at its input port and the we check its output port for desired results. We change the input again to cover possible combination(s) and check the output again. We continue doing it, till we exhaust all possible inputs. If output under all conditions is as expected, the circuit stands verified.

Here is how a stimulus verification code looks like

  1. `timescale 1ns / 1ps
  2. module stimulus;
  3. // Inputs
  4. reg x;
  5. reg y;
  6. // Outputs
  7. wire z;
  8. // Instantiate the Unit Under Test (UUT)
  9. comparator uut (
  10. .x(x),
  11. .y(y),
  12. .z(z)
  13. );
  14.  
  15. initial begin
  16. // Initialize Inputs
  17. x = 0;
  18. y = 0;
  19.  
  20. // Wait 100 ns for global reset to finish
  21. #100;
  22. #50 x = 1;
  23. #60 y = 1;
  24. #70 y = 1;
  25. #80 x = 0;
  26.  
  27. end
  28.  
  29. initial begin
  30. $monitor("x=%d,y=%d,z=%d \n",x,y,z);
  31. end
  32.  
  33. endmodule
  34.  
  35.  


Let us now try to understand the individual pieces of the code. The code


`timescale 1ns / 1ps

 
defines the timescale. It tells that the simulation will run in steps of 1ns and has a precision value of 1ps. We will come back to it later.

The following section of the code defines the values of the input at different interval of time.

  1. initial begin
  2. // Initialize Inputs
  3. x = 0;
  4. y = 0;
  5.  
  6. // Wait 100 ns for global reset to finish
  7. #100;
  8. #50 x = 1;
  9. #60 y = 1;
  10. #70 y = 1;
  11. #70 x = 0;
  12. end


Initially the value of x and y are both 0. We wait for 100 ns to allow the global reset to finish. At t = 50 ns , we assign the value of x as 1. So at t = 50 ns we have x =1 and y = 0. At t = 60 ns we assign the value of y as 1. So at t = 60 ns we have x =1 and y =1. So and and so forth. At each step, the value of the out z changes in accordance with the design and this is what we need to verify.

The code monitor the values of x, y and z at EACH change.

  1. initial begin
  2. $monitor("x=%d,y=%d,z=%d \n",x,y,z);
  3. end


It will basically display the values of x, y and z as follows.

x=0,y=0,z=1 
x=1,y=0,z=0 
x=1,y=1,z=1 
x=0,y=1,z=0 

 

In the next page we will see how to test this code using the simulation with Xilinx tool.