Difference betweern Synchronous and Asynchronous reset in D Flip Flop |
What are advantages and disadvantages of Synchronous and Asynchronous reset in D Flip Flop
In asynchronous reset the Flip Flop does not wait for the clock and sets the output right at the edge of the reset. In Synchronous Reset, the Flip Flop waits for the next edge of the clock ( rising or falling as designed), before applying the Reset of Data. The major differences are
1. The Asynchronous implementation is fast, as it does not has to wait for the clock signal to be applied. The adds only slight advantage in timing that too at the time of reset.
2. In Synchronous implementation, we must make sure that the reset signal stays low ( or high as programmed) for it to take effect. If the duration is too short, it may miss the next rising or falling edge of clock.
3. The asynchronous reset can lead to metastability issues. To understand the metastability issue consider that the clock rising edge comes right after the reset edge. The D flip Flop must have certain minimum time between reset edge and clock edge, called reset recovery time. If this time duration is violated, the output is not guaranteed. With synchronous implementation, this issue does not happen.