## Binary Counter using verilog

A binary counter is a simple counter that has an initial value of 0 at the time of reset. It value keeps incrementing by 1 at each clock cycle. And finally it reaches its maximum value, say 1111 in binary for a 4 bit counter, it again reaches 0000 in binary and keeps counting one.

Here is the verilog implemmentation of shift register.

 `// referencedesigner.com// Example of binary_countermodule binary_counter #(parameter N=4) ( input wire clk, reset, output wire [N-1:0] binary );  reg [N-1:0] r_reg; wire [N-1:0] r_next;  always @(posedge clk, negedge reset) begin if (~reset) r_reg <= 0; else r_reg <= r_next; end assign binary = r_reg; assign r_next = r_reg+1;endmodule`

## Explanation

We make use of the simple addition statement for incrementing value. We should note the property of addition that - it wraps when it reaches its max value.

 `assign r_next = r_reg+1;;`

The testbech for the binary counter

 ``timescale 1ns / 1psmodule stimulus; // Inputs reg clk ; reg reset; // Output wire[3:0] binary; // Instantiate the Binary Counter binary_counter #(4) s1 ( .clk(clk), .reset(reset), .binary(binary) );  integer i; initial begin  clk = 0; for(i =0; i<=40; i=i+1) begin #10 clk = ~clk; end end initial begin \$dumpfile("test.vcd");\$dumpvars(0,stimulus); reset =1;#2 reset = 0;#2 reset =1;end   initial begin \$monitor("clk=%d binary=%4b",clk,binary); end endmodule`

Exercise

1. Change the binary counter so that it counts down in place of count up

2. Modify the code so that, it gives output 1 ( define another output wire), for one clock period every time it reaches max value.