Full case and parallel case


In writing casez and casex statements, the item expressions do not need to include all possible values of expression. It is possible that some values be matched more than once. As an example in the code

casez  (sel)
3'bl0l : A  =  l'bl ;
3'bl??:  A  =  l'bO;
3'bOOO:  A  =  l'bl;
endcase




the value 3'b101 will match twice ( once in 3'b101 and 3'b1??). However, the one that matches
first takes effect and hence the value of A is assigned as 1'b1. 


Another thing to note is that, some values do not match. For example there is no match for 3'b010. In such case the previous value is preserved.

When all possible binary values of the expression are covered by the item expressions, the statement is known as a full case statement.

we must use a full case statement in all combinational circuit, since each input combination should have an output value. A default item to cover all the unmatched values. For example, the previous statement can be revised either as

casez  (sel)
3'bl0l : A  =  l'bl ;
3'bl??:  A  =  l'bO;
3'bOOO:  A  =  l'bl;
default: A =   1'b'x;
endcase



A gets a don't care value when no match occur. 




In the above example, the expressions are not mutually exclusive. The 3'b101 apprears twice. If we macke the item expressions in case statements mutually exclusive, it is called a parallel case statement. Following is an example of parallel case statement
  1. // Referencedesigner.com
  2. // Priority Encoder Example - Usage of case
  3. // Verilog Tutorial
  4.  
  5. module priory_encoder_case
  6. (
  7. input wire [4:1] x,
  8. output reg [2:0] pcode
  9. );
  10. always @ *
  11.  
  12. case (x)
  13. 4'b1000, 4'b1001 , 4'b1010, 4'b1011 , 4'b1100 , 4'b1101, 4'b1110 , 4'b1111 :
  14. pcode = 3'b100;
  15. 4'b0100, 4'b0101 , 4'b0110, 4'b0111 :
  16. pcode = 3'b011 ;
  17. 4'b0010, 4'b0011 :
  18. pcode = 3'b010;
  19. 4'b0001 :
  20. pcode = 3'b001;
  21. 4'b0000 :
  22. pcode = 3'b000;
  23. endcase
  24.  
  25. endmodule


From synthesis point of view, a parallel case statement infers a multiplexing routing network. A non-parallel case statement usually infers a priority routing network.