Verilog $monitor



Verilog provides some system tasks and functions specifically for generating input and output to help verification. $monitor is one such system task. These system tasks are not used ( or ignored ) by the sysnthesis tools.

Syntax of $monitor statment



A monitor statement has the syntax of

		
$monitor ("format_string", parameter1, parameter2, ... );	


Where the "format_string", specifies how the parameters will be displayed.If you are familiar with C/ C++ programming, then you wll note that the format string has exactly the same format structure of format string in C / C++.

$monitor displays the values of its parameters EVERY time ANY of its parameter changes value.

We may have numerical, hexadecimal or binary outputs. The parameter1,parameter2 ... etc are the list of the variables that need to be printed.

Some examples



1. %d will print the variable in decimal
2. %4b will print the varilable in binary - that has width of 4.
3. %h will print the variable in hexadecimal.


The monitor statement is not as powerful as the graphics waveform tools, but are handy in many instances and will be used quite a bit throughout this tutorial.

  1. `timescale 1ns / 1ps
  2. //////////////////////////////////////////////////////////////////////////////////
  3. // Company: referencedesigner.com
  4. //////////////////////////////////////////////////////////////////////////////////
  5. module comparator2bit(
  6. input [1:0] x,
  7. input [1:0] y,
  8. output z
  9. );
  10.  
  11. assign z = (x[0] & y[0] & x[1] & y[1]) |
  12. (~x[0] & ~y[0] & x[1] & y[1]) |
  13. (~x[0] & ~y[0] & ~x[1] & ~y[1])|
  14. (x[0] & y[0] & ~x[1] & ~y[1]);
  15. endmodule
  16.  
  17.  




  1.  
  2. `timescale 1ns / 1ps
  3. module stimulus;
  4. // Inputs
  5. reg x;
  6. reg y;
  7. // Outputs
  8. wire z;
  9. // Instantiate the Unit Under Test (UUT)
  10. comparator uut (
  11. .x(x),
  12. .y(y),
  13. .z(z)
  14. );
  15.  
  16. initial begin
  17. $dumpfile("test.vcd");
  18. $dumpvars(0,stimulus);
  19. // Initialize Inputs
  20. x = 0;
  21. y = 0;
  22.  
  23. #20 x = 1;
  24. #20 y = 1;
  25. #20 y = 0;
  26. #20 x = 1;
  27. #40 ;
  28.  
  29. end
  30.  
  31. initial begin
  32. $monitor("t=%3d x=%d,y=%d,z=%d \n",$time,x,y,z, );
  33. end
  34.  
  35. endmodule
  36.  
  37.  




This produces the following result in console
 
x=0,y=0,z=1 

x=1,y=0,z=0 

x=1,y=1,z=1 

x=1,y=3,z=0 

x=3,y=3,z=1 

If we change the $monitor statement to, for example
 
$monitor("x=%2b,y=%2d,z=%b \n",x,y,z);


The output will change to

 
x=00,y= 0,z=1

x=01,y= 0,z=0

x=01,y= 1,z=1

x=01,y= 3,z=0

x=11,y= 3,z=1

You can append b, h, o to $monitor to change default format to binary, octal or hexadecimal. Consider the vector example again. However, if we change

$monitor("x=%d,y=%d,z=%d \n",x,y,z);

to

$monitorb("x=",x, " y=",y," z= ",z);

It will produce the following output
 
x=00 y=00 z= 1
x=01 y=00 z= 0
x=01 y=01 z= 1
x=01 y=11 z= 0
x=11 y=11 z= 1

Another similar statement similar to $monitor is $display. Whereas, $monitor displays the result everytime its parameter changes, the $display statement displays content only once when it is called. As an example following code would have to be written to achieve same result.

  1. #50 x =2'b01;$display("x=%h,y=%h,z=%h \n",x,y,z);
  2. #50 y =2'b01;$display("x=%h,y=%h,z=%h \n",x,y,z);
  3. #50 y =2'b11;$display("x=%h,y=%h,z=%h \n",x,y,z);
  4. #50 x =2'b11;$display("x=%h,y=%h,z=%h \n",x,y,z);